High frequency digital-to-analog converters (DAC) are essential components for modern communication systems like DOCSIS, WiHD, etc. Indeed, DAC performance requirements are increasing with each new generation of these modern standards.
More particularly for high speed and high resolution applications, current steering DACs are preferred. A current steering DAC works by applying a digital data sequence on a clock edge to control or steer the current between two branches of an output differential pair of transistors. As a result, a current proportional to the input digital sequence is produced and passed through differential load resistors to generate the analog output voltage. This current steering process involves a current source coupled with plurality of transistor switches connecting to the output. Current delivered to the output is determined by the current source and mismatch of the current steering switches.
For the design of current steering digital to analog converters there are three major components which dominate the performance of the converter: a) the accuracy of weights of the current sources because each one represents a binary or thermometric weight corresponding to the input bit of the binary sequence; b) the total parasitic capacitance at key nodes in the current signal path and c) control signal timing mismatch and inter symbol interference because not every switch is toggled on each clock transition (this makes the output voltage sensitive to the frequency of the output signal and results in distortion at high output frequency). The weight accuracy concern is responsible for the static or DC performance of the DAC design. The parasitic capacitance concern is responsible for high frequency performance of the DAC.
Current source mismatch error is reduced by increasing the area of transistor used to make the current source. However, there is a tradeoff for increasing the area of the transistor in that node capacitance is also proportionally increased. As a result, high frequency performance is reduced when using larger transistors as current sources. There is accordingly a need to minimize the area occupied by the current source in current steering implementations so as to reduce parasitic capacitance for good high frequency performance. However, the reduction of the area of the current source increases a resultant mismatch with the switching transistors used for current steering, this factor becoming a more dominant component affecting accuracy of the current source.
There is also an issue related to inter-symbol interference in this kind of architecture as all binary current sources will not switch every time so some capacitive nodes need time to settle and some unsettled nodes have memory effect resulting in dynamic performance degradation. To improve the dynamic performance of the DAC and to eliminate inter-symbol interference, two pairs of switches are instead used for current steering. This type of DAC circuit configuration is referred to in the art as a quad switch circuit. The design of the quad switch configuration ensures that there is some switching at every clock cycle for all capacitive nodes and hence all nodes show a same behavior at all output frequencies. However, quad switches have some mismatch and they introduce different voltages at the nodes when switched on. Since the current sources are now small transistors, these devices see change in drain to source voltages and hence the current changes during each clock phase degrading the static performance.
Calibration of the current source and included switch transistors is accordingly needed.
Digital-to-analog converters are well known circuits in the art. The following references illustrate and describe examples of current state-of-the-art digital-to-analog converters:    W. Tseng, et. al. “A 12b 1.25 GS/s DAC in 90 nm CMOS with >70 dB SFDR up to 500 MHz” ISSCC2011;    Gil Engel, et. al., “A 14b 3/6 GHz Current-Steering RF DAC in 0.18 μm CMOS with 66 dB ACLR at 2.9 GHz” ISSCC2012;    W. Lin, et. al., “A 12b 1.6 GS/s 40 mW DAC in 40 nm CMOS with >70 dB SFDR over Entire Nyquist Bandwidth” ISSCC2013;    Brian Brandt, et. al., “A 14b 4.6 GS/s RF DAC in 0.18 μm CMOS for Cable Head-End Systems” ISSCC2014;    Hans Van de Vel, et. al., “A 240 mW 16b 3.2 GS/s DAC in 65 nm CMOS with <−80 dBc IM3 up to 600 MHz” ISSCC2014; and    U.S. Pat. No. 8,125,361.
The disclosures of these references are incorporated by reference.